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NCP372 Positive and Negative Overvoltage Protection Controller with Internal Low Ron NMOS FETs and Status FLAG
The NCP372 is able to disconnect systems from its output pin when wrong operating conditions are detected at it's input. The system is both positive and negative overvoltage protected up to 28 V. This device uses internal NMOS, and therefore, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP372 is able to instantaneously disconnect the output from the input, due to integrated Low Ron Power NMOS, if the input voltage exceeds the overvoltage threshold (OVLO) or undervoltage threshold (UVLO). At powerup (EN pin = low level), the Vout turns on 30 ms after the Vin exceeds the undervoltage threshold. The NCP372 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD-protected input (15 kV Air) when bypassed with a 1.0 mF or larger capacitor.
Features
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1
12 PIN LLGA MU SUFFIX CASE 513AK
NCAI 372 ALYWG G
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
IN IN GND RES RES RES
1 2 3 4 5 6 12 OUT 11 10 9 8 7
* * * * * * * * * * * * * * * * * * *
Overvoltage Protection up to 28 V Negative Voltage Protection down to -28 V Reverse Current Blocking On-Chip Low RDS(on) NMOS Transistor: Typical 130 mW Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Soft-Start Alert FLAG Output Shutdown EN Input Compliance to IEC61000-4-2 (Level 4) 8.0 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B Human Body Model = 2 12 Lead LLGA 3x3 mm Package This is a Pb-Free and Halogen-Free Device Cell Phones Camera Phones Digital Still Cameras Personal Digital Assistant MP3 Players GPS
1
OUT FLAG EN NC GND
NCP372
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
Applications
(c) Semiconductor Components Industries, LLC, 2009
April, 2009 - Rev. 0
Publication Order Number: NCP372/D
NCP372
TYPICAL APPLICATION CIRCUIT AND FUNCTIONAL BLOCK DIAGRAM
10k Charger Wall Adapter U1 1 2 3 4 5 6 12 IN OUT 11 IN OUT 10 GND FLAG 9 RES EN 8 NC 7 RES RES GND NCP372 0
FLAG EN FLAG 4.7mF EN
System LI+BATTERY
1mF
GND
Figure 1. Typical Application Circuit
INPUT Gate Driver
OUTPUT
VREF Charge Pump
EN Block
UVLO OVLO
Control Logic and Timer FLAG
Thermal Shutdown
EN
Figure 2. Functional Block Diagram
GND
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NCP372
PIN FUNCTION DESCRIPTION
Pin 1, 2 Name IN Type POWER Description Input voltage pins. These pins are connected to the power supply. A 1 mF low ESR ceramic capacitor, or larger, must be connected between these pins and GND. The two IN pins must be hardwired to common supply. Main Ground Reserved pin. This pin must be connected to GND. Reserved pin. This pin must be connected to GND. Reserved pin. This pin must be connected to GND. This pin must be directly hardwired to GND or through a pull down resistor with a 1 MW maximum value. Not Connected Enable Pin. The device enters into shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull-down or to an I/O pin. This pin does not have an impact on the fault detection. Fault Indication Pin. This pin allows an external system to detect fault condition. The pin goes low when input voltage exceeds OVLO threshold, drops below UVLO threshold, or internal temperature exceeds thermal shutdown limit. Since the pin is open drain functionality, an external pull up resistor to VBat must be added (10 kW minimum value). Output Voltage Pin. This pin follows IN pins when "no input fault" is detected. The output is disconnected from the VIN power supply when the input voltage is under the UVLO threshold or above OVLO threshold or thermal shutdown limit is exceeded. The PAD1 is used to dissipate the internal MOSFET thermal energy and must be soldered to an isolated PCB area. The area must not be connected to any potential other than a completely isolated one. See PCB Recommendations on page 10.
3 4 5 6 7 8 9
GND RES RES RES GND NC EN
POWER INPUT INPUT INPUT POWER NC INPUT
10
FLAG
OUTPUT
11,12
OUT
OUTPUT
13
PAD1
POWER
MAXIMUM RATINGS
Rating Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (IN to GND) Maximum Voltage (OUT to GND) Maximum Voltage (All others to GND) Thermal Resistance, Junction-to-Air, (Note 1) Operating Ambient Temperature Range Storage Temperature Range Junction Operating Temperature ESD Withstand Voltage (IEC 61000-4-2) Human Body Model (HBM), Model = 2, (Note 2) Machine Model (MM) Model = B, (Note 3) Moisture Sensitivity Symbol Vminin Vmin Vmaxin Vmaxout Vmax RqJA TA TSTG TJ Vesd Value -30 -0.3 30 10 7 200 -40 to +85 -65 to +150 150 15kV air, 8kV contact 2000V 200V Level 1 Unit V V V V V C/W C C C kV V V
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The RqJA is highly dependent on the PCB heat sink area (connected to PAD1). See PCB recommendation paragraph. 2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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NCP372
ELECTRICAL CHARACTERISTICS (Vin = 5 V, Minimum/Maximum limits at -40C < TA < +85C unless otherwise noted. Typical
values are at TA = +25C) Characteristics Input Voltage Range Input Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Over voltage Lockout Threshold NCP372MUAITXG Overvoltage Lockout Hysteresis Vin to Vout Resistance Symbols Vin Vinmin UVLO UVLOhyst OVLO OVLOhyst RDS(on) Conditions EN = low or high, Vout = 0 V EN = low or high, Vout = 4.25V Vin falls below UVLO Threshold Vin rises above UVLO Threshold + UVLOhyst Vin rises above OVLO threshold Vin falls below to OVLO - OVLOhyst Vin = 5 V, EN = low, Load Connected to Vout Vin = 5 V, EN = low, Load Connected to Vout @ 25C No Load. EN = high, Vin connected 25C Overtemperature Range Output Load, Vin = 5.5 V, EN = low 1.2 V < Vin < UVLO Sink 50 mA on FLAG Pin Vin > OVLO, Sink 1 mA on FLAG Pin FLAG Leakage Current EN Voltage High EN Voltage Low EN Leakage Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis TIMINGS Start Up Delay FLAG Going Up Delay Turn Off Delay Alert Delay Disable Time NOTE: ton tstart toff tstop tdis From Vin > UVLO to Vout w 0.3 V From Vout > 0.3 V to FLAG = 1.2 V From Vin > OVLO to Vout v 0.3 V Vin Increasing from 5 V to 8 V at 3 V/ms From Vin > OVLO to FLAG v 0.4 V See Figure 3 and 9 Vin Increasing from 5 V to 8 V at 3 V/ms EN = 0.4 V to 1.2 V to Vout v 0.3 V 20 20 30 30 1.5 1.5 2.5 40 40 5.0 ms ms ms ms ms FLAGleak VihEN VilEN ENleak TSD TSDHYST Vin connected Vin disconnected 200 1.0 150 30 FLAG Level = 5.5 V 1.2 0.55 1.0 1.3 30 400 400 nA V V nA C C Min -28 -24 2.6 45 6.0 60 2.7 60 6.3 80 130 130 90 200 2.8 75 6.6 100 220 200 170 260 310 mA mA A mV Typ Max 28 Unit V V V mV V mV mW
Input Standby Current Input Supply Quiescent Current Minimum DC Current FLAG Output Low Voltage
IddSTD IddIN ICHG Volflag
Electrical parameters are guaranteed by correlation across the full range of temperature.
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NCP372
TIMING DIAGRAMS
Vin
UVLO ton
Vout
0.3 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
EN EN Vout Vin - (RDS(on) FLAG 1.2 V tdis I) 0.3 V FLAG Vin
1.2 V OVLO UVLO ton + tstart
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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NCP372
TYPICAL OPERATING CHARACTERISTICS
Figure 7. ton, tstart, EN = low (10 ms/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG)
Figure 8. tstart, EN = low (10 ms/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG)
Figure 9. Vin rise to fault (400 ns/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG)
Figure 10. Vin rise to fault (100 ms/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG)
Figure 11. Disable time (200 ms/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG, Ch4: EN)
Figure 12. EN on & off (200 ms/div, Ch1: Vin, Ch2: Vout, Ch3: FLAG, Ch4: EN)
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NCP372
TYPICAL OPERATING CHARACTERISTICS
200 180 160 140 RDS(on) (mW) 120 100 80 60 40 20 0 -50 0 50 TEMPERATURE (C) 100 150 RDS(on) (mW) EN = low 250 200 150 100 50 0 2.5 300 EN = low
3.5
4.5 Vin (V)
5.5
6.5
7.5
Figure 13. RDS(on) vs. Temperature
Temp=- 40C 800 600 400 C Temp=-25
Figure 14. RDS(on) vs. Vin
Temp= 25C Temp= 85C Temp 125C =
Iq vs Vin @ Vout open (/EN=low)
C Temp= 0
Iq (mA)
200 0 -200 -400 -30
-20
-10
Vin (V)
0
10
20
30
Figure 15. Quiescent Current vs. Vin from -30 V to +30 V, Enable Mode
Temp=- 40C 800 600 400
C Temp=-25
Iq vs Vin @ Vout open (/EN= high)
C Temp= 0 Temp= 25C
Temp= 85C
Temp 125C =
Iq (mA)
200 0 -200 -400 -30
-20
-10
Vin (V)
0
10
20
30
Figure 16. Quiescent Current vs. Vin from -30 V to +30 V, Disable Mode http://onsemi.com
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NCP372
Operation The NCP372 provides overvoltage protection for positive and negative voltages, up to 28 V or down to -28 V. The negative protection is ensured by an internal Low RDS(on) NMOS FET. A second internal Low RDS(on) NMOS FET protects the systems (i.e.: charger) connected on the Vout pin, against positive overvoltage. At powerup, with EN pin = low, the output rises ton seconds after the input overtakes the undervoltage UVLO (Figure 3). The NCP372 provides a FLAG output, which alerts the system that a fault has occurred. The FLAG signal rises tstart seconds after the output signal rises. FLAG pin is an open drain output. Undervoltage Lockout (UVLO) To ensure proper operation under any condition, the device has a built-in undervoltage lockout (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is 2.7 V nominal. The FLAG output remains low as long as Vin does not reach UVLO threshold. This circuit has a built in hysteresis to provide noise immunity to transient conditions. Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built-in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled until the input voltage exceeds 6.3 V. FLAG output remains low until Vin is higher than OVLO. This circuit has a built in hysteresis to provide noise immunity to transient conditions. FLAG Output The NCP372 provides a FLAG output, which alerts external systems that a fault has occurred. This pin goes low as soon the OVLO threshold is exceeded or when the Vin level is below the UVLO threshold. When Vin level recovers normal condition, FLAG goes high, after tstart delay following the output response. The pin is an open drain output, thus a pullup resistor (typically 1.0 MW, minimum 10 kW) must be provided to VCC. The FLAG level always reflects Vin status, even if the device is turned off (EN = 1). EN Input To enable normal operation, the EN pin shall be forced low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. Negative Voltage and Reverse Current The built-in NMOS protects the downstream system from negative voltages occurring on IN pin down to -28 V. The same NMOS avoids reverse currents that could discharge the battery. When a fault occurs, the output is disconnected from IN pin and FLAG goes low.
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NCP372
Vout = 0 FLAG = Low Reset Timer
Vin < UVLO or Vin > OVLO
Vout = 0 FLAG = Low Timer Count
OVLO > Vin > UVLO T < ton
Timer Check
T = ton
Reset Timer
Vin < UVLO or Vin > OVLO
Check Vin FLAG = Low Timer Count UVLO < Vin < OVLO
EN = 1 Vout = Open Check EN
EN = 0 Vout = Vin
Vin < UVLO or Vin > OVLO
Timer Check
T < tstart
T = tstart
UVLO < Vin < OVLO
Check EN
UVLO < Vin < OVLO
EN = 1 Vout = Open FLAG = High Check Vin
EN = 0 Vout = Vin FLAG = High Check Vin Vin < UVLO or Vin > OVLO
Figure 17. State Machine
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NCP372
Thermal Shutdown protection PCB Recommendations
In case of internal overheating, the integrated thermal shutdown protection turns off the internal MOSFETs in order to instantaneously decrease the device temperature. The thermal threshold has been set at 150C FLAG then goes low to inform the MCU. As the thermal hysteresis is 30C, the MOSFETs will turn on as soon the device temperature falls below 120C. If the fault event is still present, the temperature increase engages the thermal shutdown again until the fault event disappears.
Since the NCP372 integrates the 1.3A N-MOSFETs, PCB rules must be respected to properly evacuate the heat out of the silicon. From an applications standpoint, PAD1 of the NCP372 package should be connected to an isolated PCB area to increase the heat transfer if necessary. In any case, PAD1 should be not connected to any other potential or GND other than the isolated extra copper surface. To assist in the design of the transfer plane connected to PAD1, Figure 18 shows the copper area required with respect to RqJA.
2.5
250 200 150 100 50 0 qJA Curve with PCB cu thk 2 oz qJA Curve with PCB cu thk 1 oz 400 500 600 Power Curve with PCB cu thk 2 oz
MAXIMUM qTA (C/W)
2 1.5 1 0.5 0 700
Power Curve with PCB cu thk 1 oz
0
100
200
300
COPPER HEAT SPREAD AREA (mm2)
Figure 18. Copper heat Spread Area ESD Tests
The NCP372 conforms to the IEC61000-4-2, level 4 on the Input pin. A 1 mF (I.E Murata GRM188R61E105KA12D) must be placed close to the IN pins. If the IEC61000-4-2 is not a requirement, a 100 nF/25 V must be placed between IN and GND. The above configuration supports 15 kV (Air) and 8 kV (Contact) at the input per IEC61000-4-2 (level 4). Please refer to Figure 19 for the IEC61000-4-2 electrostatic discharge waveform.
Figure 19. Ipeak = f(t)/IEC61000-4-2
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NCP372
RDS(on) and Dropout
The NCP372 includes two internal low RDS(on) N-MOSFETs to protect the system, connected on OUT pin, from overvoltage, negative voltage and reverse current protection. During normal operation, the RDS(on) characteristics of the N-MOSFETs give rise to low losses on Vout pin.
ORDERING INFORMATION
Device NCP372MUAITXG Marking NCAI 372
As example: Rload = 8 W, Vin= 5 V. RDS(on) = 155 mW. Iout = 800 mA. Vout = 4.905 V NMOS Losses = RDS(on) x Iout2 = 0.155 x 0.82 = 0.0992 W
Package LLGA12 (Pb-Free)
Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP372 can be available in several undervoltage and overvoltage options. Part number is designated as follows:
NCP372MUxxTxG
ab c d Code a b c d Contents UVLO Typical Threshold a: A = 2.7 V OVLO Typical Threshold b: I = 6.3 V Tape & Reel Type c: X = 3000 d: G = Pb-Free
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NCP372
PACKAGE DIMENSIONS
LLGA12 3x3, 0.5P CASE 513AK-01 ISSUE O
D AB
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 3.00 BSC 2.60 2.80 3.00 BSC 1.90 2.10 0.50 BSC 0.20 --- 0.25 0.35
2X
0.15 C
2X
0.15 C
0.10 C A
12X
0.08 C
A1
12X
K
12X
L
The products described herein (NCP372), may be covered by one or more U.S. patents. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
CCC CCC CCC
1 12
PIN ONE REFERENCE
E
TOP VIEW
SOLDERING FOOTPRINT*
SIDE VIEW D2
6
C
SEATING PLANE 1
3.30
12X
0.50 0.50 PITCH 2.75
e
0.43
E2
11X
0.30
7 12X
2.05
DIMENSIONS: MILLIMETERS
b
0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP372/D

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